In digital hard-wired transmission systems, digital data in the form of square-wave or trapezoidal pulses is fed into a transmission cable, usually a copper cable or a fibre-optic cable, and is received by a receiver at the other end of the cable. When this is done, the data signal becomes attenuated in respect of amplitude and distorted in respect of phase angle and group transit time as a result of being transmitted, in which case it may also have high-frequency and low-frequency interference superimposed on it. The distorted incoming signal at the receiver must therefore be amplified and freed of distortion in the receiver before any reconstruction or recovery is possible of the data which was transmitted in the form of the data signal. For this purpose, known receivers comprise an amplifier at the input end, a distortion remover (equalizer) connected downstream of the amplifier, a clock-signal recovery unit for regenerating or recovering the clock signal belonging to the data transmitted and a data reconstruction unit for reconstructing the data originally transmitted, a data stream synchronised with the regenerated or recovered clock signal being produced by the data reconstruction unit. The clock-signal recovery and data reconstruction units dealt with above are usually combined into a circuit which is referred to as a clock and data recovery (CDR) unit.
What has predominantly been used to date for clock-signal recovery and data reconstruction has been a CDR unit produced in mixed-signal circuit technology which thus has both analog and digital circuit components, it being the analog data signal which has previously been equalized or filtered which is fed to this CDR unit. In the CDR unit, this data signal is assessed for its phase, for example, by an analog phase detector based on switched-capacitor circuit technology, to enable the clock signal of the transmitted data to be derived therefrom with the help of a suitable phase-locked loop. This principle is based on over-sampling of the received data signal and thus results in stringent demands being made on the analog circuitry. What is more, the entire data signal is needed for assessment on this principle, and the amplitude of the data signal also has to be stable.
In CDR circuits of purely digital design, the received data signal is first digitised with the help of a comparator, with the CDR circuit which follows the comparator assessing only the edges of the digitised data signal, to enable the clock signal of the transmitted data to be regenerated with the help of a digital phase-locked loop. However, CDR circuits of purely digital design often cause relatively extreme abrupt phase shifts within the CDR circuit, as a result of which the jitter requirements laid down by the particular data transmission standard may, under certain circumstances, not be satisfied.
A further approach to a solution is shown diagrammatically in FIG. 2.
What is shown in this case is a CDR circuit 1 of digital design for recovering a clock signal and regenerating data from a received data signal RX. The digital CDR unit 1 regenerates the clock signal of the data originally transmitted using a digital phase-locked loop to which the digitised data signal RX is fed as a reference signal, thus enabling the data originally transmitted DATA to be reconstructed from the received data signal RX by using the clock signal which has been regenerated in this way.
Provided in transceivers is not only a receiving section having a CDR unit of the kind described above but also a transmitting section for transmitting data at a given clock frequency. Associated with this transmitting section is a unit 17 referred to as a clock synthesizer unit which derives the transmission clock signal fTX for the transmission of data as a function of the clock signal regenerated by the CDR unit 1. In a similar way to the CDR unit, this CSU unit generally comprises a phase-locked loop to which the clock signal recovered by the CDR unit 1, or a clock signal fCLK derived therefrom, is fed as a reference clock signal. Due to the demanding requirements which the CSU unit 17 is called upon to meet in respect of intrinsic jitter, there is provided in the known solution shown in FIG. 2 a further phase-locked loop (PLL) 3 to attenuate jitter, which loop conditions the clock signal recovered by the CDR unit 1 and frees it of jitter before the de-jittered clock signal fCLK is fed to the CSU unit 17 for generating the transmission clock signal fTX. The phase-locked loop 3 may be designed using mixed-signal circuit technology.
In the example shown in FIG. 2, there is also a multiplexer 16 provided by means of which an external reference clock signal fTXEXT can be selected as a reference clock signal for the CSU unit 17 in place of the clock signal fCLK emitted by the phase-locked loop 3. The external clock signal fTXEXT may, for example, be a clock signal which, although it originates from the clock signal recovered by the CDR unit 1, has been produced externally.
The disadvantage of the solution shown in FIG. 2 lies in the fact that a total of three phase-locked loops are required, which means that implementation is relatively costly and complicated and the area and power required are relatively large. Also, the sensitivity of the circuit shown in FIG. 2 to noise and internal and external sources of interference is relatively great due to the lack of insulation between the individual phase-locked loops.
The demands made on the clock-signal recovery and data reconstruction that arise from the data transmission standard which is implemented in the given case are generally high. In this way, the clock-signal recovery has to proceed reliably even with data strings in which there are long sequences of zeroes or in which there is no change of edge for a long period (so-called NRZ (non-return-to-zero) data). The jitter tolerance and bit error rate (BER) laid down by the particular data transmission standard have to be observed. With regard to the clock-signal generation carried out by the CSU unit, stringent requirements have to be met in respect of jitter suppression or low intrinsic jitter. Generally speaking, the clock-signal recovery and data reconstruction should work for both scrambled data and unscrambled data.
Particularly demanding requirements have to be met by the stability of the clock signal or frequency in the event of the received data signal, i.e. the incoming data stream, not being present at all or not being of a sufficiently high level or there not being a sufficiently large number of transmissions (the so-called “loss-of-signal” state), which means that reliable recovery of the clock signal or reconstruction of the data by analysing the received data signal is prevented in the CDR unit. What in particular has to be ensured in this case is that the phase-locked loop contained in the CDR unit continues to run even if this loss-of-signal error state occurs.